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    AVRnet V1.1 is out, added UDP bootloader support for firmware upgrade purpose. You can upgrade new firmware by using AVRnet CPanel V1.1.



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Portal to AVR Resources and Community!
    Welcome to AVRportal.com!
AVRportal.com is the resources and community for poeple who used AVR microcontroller and articles about microcontroller, electronics, computer.

It is believed the AVR basic architecture was conceived by two students at the Norwegian Institute of Technology (NTH) Alf-Egil Bogen and Vegard Wollan.

The original AVR MCU was developed at a local ASIC house in Trondheim Norway, where the two founders of Atmel Norway were working as students. It was known as a uRISC (Micro RISC). When the technology was sold to Atmel, the internal architecture was further developed by Alf and Vegard at Atmel Norway, a subsidiary of Atmel founded by the two architects.

The acronym AVR has been reported to stand for Advanced Virtual RISC, but it has also been rumoured to stand for the initials chip's designers: Alf and Vegard [RISC]. Atmel says that the name AVR is not an acronym and does not stand for anything in particular.

Note that the use of "AVR" in this article generally refers to the 8-bit RISC line of Atmel AVR Microcontrollers.

Among the first of the AVR line was the AT90S8515, which in a 40-pin DIP package has the same pinout as an 8051 microcontroller, including the external multiplexed address and data bus. The polarity of the /RESET line was opposite (8051's having an active-high RESET, while the AVR has an active-low /RESET), but other than that, the pinout was identical. (from Wikipedia).


AVR Architecture


to maximize performance and parallelism, the AVR uses a Harvard architecture – with separate memories and buses for program and data. Instructions in the program memory are executed with a single level pipelining. While one instruction is being exe- cuted, the next instruction is pre-fetched from the program memory. This concept enables instructions to be executed in every clock cycle. The program memory is In- System Reprogrammable Flash memory.


Single level pipelining

the parallel instruction fetches and instruction executions enabled by the Harvard architecture and the fast-access Register File concept. This is the basic pipelin- ing concept to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost, functions per clocks, and functions per power-unit.



Development board!
    AVRnet V1.0! AVRnet is an Ethernet development board base on AVR microcontroller and ENC28J60, you can develop your internet control system or build your own small web-server by using AVRnet. AVRnet using ATMEGA32 as main processor ENC28J60 as Ethernet controller and LCD + push switch for user interface. More detail


AVRnet Ethernet dev board.


AVR JTAG AVR JTAG is a debuger/programmer for AVR microcontroller integrated with AVR Studio, debug/program via serial port or USB to Serial converter. More detail


AVR JTAG Debuger/Programmer




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